Parameterized and Programmable Low Power Soft FIR Filtering IP Cores

In this paper, the authors present implementation of a number of low power FIR filter architectures to design reuse-able, programmable and parameterized soft FIR filter IP Cores and compare their performance in terms of area and power. An overall 22.1% power saving is achieved. The paper provides an analysis of the programmable cores and the impact of their constituent components on the overall power saving with different algorithms. The paper also presents analysis of power and area overhead due to the introduction of programmability in cores. The cores are fully parameterized and dynamically programmable up to 128 taps of filter. The programming can be done by just applying a load signal and loading the new coefficients in RAM. The loading of new coefficients will completely change the personality of filter without any hardware change and in this way programmability enhances the reusability of Cores. The design of cores is technology independent. Key-words:Finite Impulse Response Filters, virtual component, reusable filter cores, virtual socket, Digital filter, DSP.